In integrated circuit fabrication, wafer throughput and wafer uniformity are critical issues. Wafer wet processes such as, for example electroplating, require precise conditions i.e. anode configuration, field shape, electrolyte composition, and the like. For high throughput wafer electroplating, wafers are typically processed in parallel using apparatus with multiple similarly configured plating baths. Batch uniformity can be difficult to maintain under such scenarios, given the multitude of factors necessary to control and reproduce, as well as the tight analytical control of plating bath composition associated with integrated circuit fabrication.
Some wafer processing apparatus are designed to address uniformity limitations. One example is the SABRE™ clamshell electroplating apparatus available from Novellus Systems, Inc. of San Jose, Calif. and described in U.S. patent application Ser. No. 08/969,984, which is herein incorporated by reference in its entirety. The SABRE™ apparatus includes three separate electroplating cells and three separate post-electrofill EBR (edge bevel removal) modules. The three separate electroplating cells receive electrolyte from a central bath, which allows for improved reproducibility in electrolytic plating conditions among the three cells. Additionally, each individual cell is configured to process wafers in essentially the same manner as the other two. Each of the three separate post-electrofill EBR modules may be employed to perform various functions such as edge bevel removal, backside etching, and acid cleaning of wafers after they have been electrofilled by one of the electroplating cells.
Although the SABRE™ tool does provide improvement in reproducibility during wafer processing, in consideration of the aforementioned issues, improved methods and apparatus could be useful. Improvement in wafer throughput and process uniformity can be rationalized in terms of the environment that a wafer is exposed to during processing. For optimum process (and thus product) uniformity in a given batch of wafers, it is logical to expose each wafer to the same environment rather than a similar environment as in parallel processing systems. This implies that sequential processing rather than parallel might offer advantages in wafer uniformity. With dedicated parallel process stations, there are separate, unique process “paths” that a wafer can take, thus increasing the variability in the finished product. Also, in typical parallel processing systems a robot arm assembly is used for wafer handling during processing. For these systems, although multiple wafers are processed simultaneously, individual plating and post-plating operations (unit operations) do not generally require the same processing time frames, often robotics handling events and software logic are difficult to balance and wafer throughput is hard to fully optimize.
There is an added dimension to the current wafer throughput and uniformity paradigm. Increasingly, technology advances in integrated circuit fabrication dictate that distinct fabrication processes are better executed in stages, rather than in one step. For example in a damascene-processing scenario, a process such as electroplating is not always simply a single step deposition process, but rather involves a set of sub-processes. In copper electroplating, after a thin seed layer of copper is applied to a wafer, copper electrofill is performed to fill the interconnect regions of the eventual circuit. This is typically done under very specific rate, electrolyte, and electric field conditions to minimize defects in the portion of the copper layer intended to form the interconnects in trenches and vias. Finally, copper is deposited at a higher deposition rate, typically under less stringent conditions, to cover the copper interconnects and fill any larger incompletely-filled features. Ideally, electroplating is performed under distinctly different conditions (temperature, electrolyte composition, electric field, etc.) at different sub-stages of the overall operation. In a conventional apparatus employing a single plating cell in which the wafer is stationary, it is difficult to attain optimal conditions for each of these electrodeposition sub-processes. Some flexibility is possible but requires changing the electrolyte composition and plating cell hardware configurations, both with associated costs in time.
Additionally, there are other throughput and uniformity issues associated with wafer processes performed before, during, and after electroplating. Non-uniform wetting fronts can cause defects in the deposited metal layer. Due to limited PVD capabilities or oxide formation, seed layers often need to be repaired before electroplating can commence. Commonly it is desirable to recover electrolyte in a rinsing step. Also, improved electropolishing techniques are being developed and used more often to supplement or replace chemical mechanical polishing. It would be advantageous to have an apparatus and methods that incorporate these processes into a single system to save time and thus optimize throughput.
What is needed therefore is improved technology for processing of semiconductor wafers in integrated circuit fabrication.